The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2015

Filed:

Nov. 09, 2012
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Xin Wang, Malta, NY (US);

Changyong Xiao, Mechanicville, NY (US);

Yue Hu, Malta, NY (US);

Yong Meng Lee, Mechanicville, NY (US);

Meng Luo, Malta, NY (US);

Jialin Weng, Clifton Park, NY (US);

Wei Hua Tong, Mechanicville, NY (US);

Wen-Pin Peng, Clifton Park, NY (US);

Assignee:

GLOBALFOUNDRIES, INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/768 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76846 (2013.01); H01L 21/28518 (2013.01); H01L 21/76831 (2013.01); H01L 21/76844 (2013.01); H01L 21/76814 (2013.01);
Abstract

Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.


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