The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2015
Filed:
Mar. 03, 2014
Applicant:
Kabushiki Kaisha Toshiba, Tokyo, JP;
Inventors:
Takeshi Sonehara, Mie, JP;
Takeshi Murata, Mie, JP;
Junya Fujita, Mei, JP;
Fumiki Aiso, Mie, JP;
Saku Hashiura, Mie, JP;
Assignee:
Kabushiki Kaisha Toshiba, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 27/115 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66825 (2013.01); H01L 21/28273 (2013.01); H01L 27/11529 (2013.01); H01L 27/11534 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 29/7881 (2013.01);
Abstract
According to one embodiment, a plurality of memory cell transistors including a floating gate and a control gate and a plurality of peripheral circuit transistors including a lower electrode portion and an upper electrode portion are included. The floating gate includes a first polysilicon region, and the lower electrode includes a second polysilicon region. The first polysilicon region is a p-type semiconductor in which boron is doped, and the second polysilicon region is an n-type semiconductor in which phosphorus and boron are doped.