The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2015

Filed:

Dec. 09, 2014
Applicant:

SK Hynix Inc., Icheon-si Gyeonggi-do, KR;

Inventors:

Jung Ryul Ahn, Namyangju-si, KR;

Jum Soo Kim, Suwon-si, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 27/108 (2006.01); H01L 49/02 (2006.01); H01L 27/105 (2006.01); H01L 27/115 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 28/60 (2013.01); H01L 21/76224 (2013.01); H01L 21/76897 (2013.01); H01L 27/105 (2013.01); H01L 27/1052 (2013.01); H01L 27/11529 (2013.01); H01L 28/90 (2013.01);
Abstract

The semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein, semiconductor memory elements formed over the semiconductor substrate in the cell region, an interlayer insulating layer formed over the semiconductor substrate in the peripheral circuit region, first conductive layers substantially vertically passing through the interlayer insulating layer, and arranged in a matrix, and second conductive layers coupling the first conductive layers in rows or columns, each pair of the second conductive layers and the first conductive layers coupled to the each pair of the second conductive layers, respectively, forming electrodes of a capacitor.


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