The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2015

Filed:

Mar. 28, 2014
Applicant:

Sandisk 3d Llc, Milpitas, CA (US);

Inventors:

Tianhong Yan, San Jose, CA (US);

Roy Edwin Scheuerlein, Cupertino, CA (US);

Assignee:

SANDISK 3D LLC, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 5/02 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 5/02 (2013.01); G11C 13/0021 (2013.01);
Abstract

A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements are each accessible by a word line in a plane and a local bit line. The three-dimensional array includes a two-dimensional array of pillar lines through the multiple layers of planes. The pillar lines are of a first type that act as local bit lines and a second type that provide access to the word lines by having respective memory elements preset to a permanently low resistance state for connecting second-type pillar lines for exclusive access to respective word lines. An array of metal lines on the substrate is switchably connected to the vertical bit lines to provide access to the local bit lines and the word lines.


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