The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2015

Filed:

Feb. 17, 2012
Applicants:

Takuya Hando, Inuyama, JP;

Masahiro Inoue, Konan, JP;

Hajime Saiki, Konan, JP;

Atsuhiko Sugimoto, Kagamigahara, JP;

Hidetoshi Wada, Komaki, JP;

Inventors:

Takuya Hando, Inuyama, JP;

Masahiro Inoue, Konan, JP;

Hajime Saiki, Konan, JP;

Atsuhiko Sugimoto, Kagamigahara, JP;

Hidetoshi Wada, Komaki, JP;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 3/40 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 21/683 (2006.01); H05K 3/46 (2006.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4007 (2013.01); H01L 21/6835 (2013.01); H01L 23/49816 (2013.01); H05K 3/4682 (2013.01); H01L 23/49822 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2221/68345 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/81192 (2013.01); H01L 2924/01084 (2013.01); H05K 3/0097 (2013.01); H05K 2201/0367 (2013.01);
Abstract

A multilayer wiring board including a build-up layer, formed from one or more conductor and resin insulation layers that are layered one on top of the other, having conductive pads formed on a surface of at least one resin insulation layer so as to project from the surface are provided. The conductive pads may each include a columnar portion situated at a lower part thereof and a convex portion situated at a higher part thereof, wherein a surface of the convex portion may assume a continual curved shape. A solder layer may be formed over an upper surface of the conductive pads. Certain embodiments make it possible to minimize or eliminate the concentration of stress on the conductive pads, and may inhibit the occurrence of defective connections to a semiconductor element and infliction of damage to the conductive pads.


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