The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 25, 2015
Filed:
Jan. 12, 2012
Naoki Tega, Kunitachi, JP;
Yasuhiro Shimamoto, Tokorozawa, JP;
Yuki Mori, Tokyo, JP;
Hirotaka Hamamura, Kodaira, JP;
Hiroyuki Okino, Kokubunji, JP;
Digh Hisamoto, Kokubunji, JP;
Naoki Tega, Kunitachi, JP;
Yasuhiro Shimamoto, Tokorozawa, JP;
Yuki Mori, Tokyo, JP;
Hirotaka Hamamura, Kodaira, JP;
Hiroyuki Okino, Kokubunji, JP;
Digh Hisamoto, Kokubunji, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A SiC MOSFET has a subject that resistance in the source region is increased when annealing for metal silicidation is performed to a source region before forming the gate insulating film, the metal silicide layer of the source region is oxidized by an oxidizing treatment (including oxynitriding treatment) when the gate insulating film is formed. When a metal silicide layer to be formed on the surface of a SiC epitaxial substrate is formed before forming a gate insulating film interface layer (oxide film), and an anti-oxidation film for the metal silicide is formed on the metal silicide layer, it is possible to suppress oxidation of the metal silicide layer by the oxidizing treatment upon forming the gate insulating film interface layer and the resistance of the source region can be decreased without lowering the channel mobility.