The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2015

Filed:

Jan. 16, 2015
Applicant:

Unisantis Electronics Singapore Pte. Ltd., Singapore, SG;

Inventors:

Fujio Masuoka, Tokyo, JP;

Masamichi Asano, Tokyo, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/01 (2006.01); H01L 27/12 (2006.01); G11C 16/08 (2006.01); H01L 27/115 (2006.01); H01L 29/78 (2006.01); H01L 29/16 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
G11C 16/08 (2013.01); H01L 27/11526 (2013.01); H01L 27/11573 (2013.01); H01L 29/16 (2013.01); H01L 29/456 (2013.01); H01L 29/7827 (2013.01);
Abstract

A semiconductor device has a smaller area. That is, in a row selection decoder including MOS transistors, which selectively connect a plurality of selection signal lines to row selection lines of NAND flash memories having an SGT structure, the MOS transistors are formed on a planar silicon layer that is formed on a substrate, and each have a structure such that a drain, a gate, and a source are disposed in the vertical direction and the gate surrounds a silicon pillar. The planar silicon layer is formed of a first activation region of a first conductivity type and a second activation region of a second conductivity type, and the first and second activation regions are connected with each other via a silicide layer formed on the surface of the planar silicon layer.


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