The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2015

Filed:

Jul. 13, 2011
Applicants:

Kwan-heum Lee, Suwon-si, KR;

Wook-je Kim, Gwacheon-si, KR;

Soon-wook Jung, Hwaseong-si, KR;

Sang-bom Kang, Seoul, KR;

Ki-hong Kim, Asan-si, KR;

Inventors:

Kwan-Heum Lee, Suwon-si, KR;

Wook-Je Kim, Gwacheon-si, KR;

Soon-Wook Jung, Hwaseong-si, KR;

Sang-Bom Kang, Seoul, KR;

Ki-Hong Kim, Asan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 29/7848 (2013.01);
Abstract

A semiconductor device and a method of manufacturing a semiconductor device are provided. In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An epitaxial layer is formed on a top surface of the substrate adjacent to the gate structure. An elevated source/drain (ESD) layer and an impurity region are formed by implanting impurities and carbon in the epitaxial layer and an upper portion of the substrate using the gate structure as an ion implantation mask. A metal silicide layer is formed on the ESD layer.


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