The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 18, 2015
Filed:
Jun. 29, 2012
Hans Weber, Bayerisch Gmain, DE;
Franz Hirler, Isen, DE;
Andreas Meiser, Sauerlach, DE;
Anton Mauder, Kolbermoor, DE;
Kurt Sorschag, Villach-Landskron, AT;
Stefan Gamerith, Villach, AT;
Roman Knoefler, Villach, AT;
Hans Weber, Bayerisch Gmain, DE;
Franz Hirler, Isen, DE;
Andreas Meiser, Sauerlach, DE;
Anton Mauder, Kolbermoor, DE;
Kurt Sorschag, Villach-Landskron, AT;
Stefan Gamerith, Villach, AT;
Roman Knoefler, Villach, AT;
Infineon Technologies Austria AG, Villach, AT;
Abstract
A semiconductor device with a dielectric layer is produced by providing a semiconductor body with a first trench extending into the semiconductor body, the first trench having a bottom and a sidewall. A first dielectric layer is formed on the sidewall in a lower portion of the first trench and a first plug is formed in the lower portion of the first trench so as to cover the first dielectric layer. The first plug leaves an upper portion of the sidewall uncovered. A sacrificial layer is formed on the sidewall in the upper portion of the first trench and a second plug is formed in the upper portion of the first trench. The sacrificial layer is removed so as to form a second trench having sidewalls and a bottom. A second dielectric layer is formed in the second trench and extends to the first dielectric layer.