The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2015

Filed:

Sep. 13, 2012
Applicants:

Eun Seok Choi, Seongnam-si, KR;

Hyun Seung Yoo, Icheon-si, KR;

Inventors:

Eun Seok Choi, Seongnam-si, KR;

Hyun Seung Yoo, Icheon-si, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/115 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11524 (2013.01); H01L 27/1157 (2013.01); H01L 27/11556 (2013.01); H01L 27/11578 (2013.01); H01L 27/11582 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01);
Abstract

A three-dimensional (3-D) nonvolatile memory device includes a support protruded from a surface of a substrate and configured to have an inclined sidewall; channel structures each configured to comprise interlayer insulating layers and channel layers which are alternately stacked over the substrate including the support, bent along the inclined sidewall of the support, wherein each of the channel structures comprises a cell region and a contact region, and the channel layers are exposed in the contact region; select lines formed over the channel structures; and a pillar type channels coupled to respective channel layers at the contact region and penetrating the select lines.


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