The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2015

Filed:

Jan. 20, 2014
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Zhen Chen, Singapore, SG;

Shen-De Wang, Hsinchu County, TW;

Yi-Shan Chiu, Taoyuan County, TW;

Wei Cheng, Singapore, SG;

Assignee:

UNITED MICROELECTRONICS CORP., Science Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 23/00 (2006.01); H01L 27/02 (2006.01); H01L 27/105 (2006.01);
U.S. Cl.
CPC ...
H01L 27/115 (2013.01); H01L 24/09 (2013.01); H01L 27/0207 (2013.01); H01L 27/1052 (2013.01); H01L 27/11524 (2013.01);
Abstract

A layout structure for memory devices includes a plurality of first gate patterns, a plurality of first landing pad patterns, a plurality of dummy patterns, a plurality of second landing pad patterns, and a plurality of second gate patterns. The first landing pad patterns are parallel with each other and electrically connected to the first gate patterns. The dummy patterns and the first landing pad patterns are alternately arranged, and the second landing pad patterns are respectively positioned in between one first landing pad pattern and one dummy pattern. The second gate patterns are electrically connected to the second landing pad patterns.


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