The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2015

Filed:

Sep. 04, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Rakesh Kumar Sinha, Bangalore, IN;

Chirag Gulati, Rajasthan, IN;

Ritu Chaba, Bangalore, IN;

Sei Seung Yoon, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/06 (2006.01); G11C 7/04 (2006.01); G11C 7/08 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G11C 7/06 (2013.01); G11C 7/04 (2013.01); G11C 7/08 (2013.01); G11C 7/227 (2013.01);
Abstract

Disclosed are various apparatuses and methods for a memory with a multiple word line design. A memory timing circuit may include a dummy word line including a first portion and a second portion and further including capacitative loading that is lumped in the second portion of the dummy word line, a first transistor connected to the first portion of the dummy word line and configured to charge the dummy word line, and a second transistor connected to the second portion of the dummy word line and configured to discharge the dummy word line. A method may include charging a dummy word line using a first transistor, and discharging the dummy word line using a second transistor, wherein the dummy word line includes a first portion and a second portion and further includes capacitative loading that is lumped in the second portion of the dummy word line.


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