The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2015

Filed:

Dec. 26, 2012
Applicants:

Hiroshi Otsuka, Tokyo, JP;

Toshiyuki Oishi, Tokyo, JP;

Yutaro Yamaguchi, Tokyo, JP;

Naoki Kosaka, Tokyo, JP;

Shinichi Miwa, Tokyo, JP;

Koji Yamanaka, Tokyo, JP;

Inventors:

Hiroshi Otsuka, Tokyo, JP;

Toshiyuki Oishi, Tokyo, JP;

Yutaro Yamaguchi, Tokyo, JP;

Naoki Kosaka, Tokyo, JP;

Shinichi Miwa, Tokyo, JP;

Koji Yamanaka, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5068 (2013.01); G06F 17/5036 (2013.01);
Abstract

A transistor characteristic calculation apparatus using a large signal equivalent circuit model has a buffer trap circuit provided between a drain terminal and a source terminal such that a parallel circuit including a resistor and a capacitor, a diode, and another parallel circuit including a resistor and a capacitor are in turn connected in series.


Find Patent Forward Citations

Otsuka, Hiroshi. (2015). Transistor characteristic calculation apparatus using large signal equivalent circuit model (U.S. Patent No. 9111061). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9111061

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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