The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2015

Filed:

Nov. 19, 2012
Applicant:

Qualcomm Technologies, Inc., San Diego, CA (US);

Inventor:

Jean-Jacques Lecler, Sunnyvale, CA (US);

Assignee:

Qualcomm Technologies, Inc., San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01); G06F 17/50 (2006.01); G06F 9/445 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 9/445 (2013.01); G06F 9/3875 (2013.01); G06F 17/505 (2013.01); G06F 2217/84 (2013.01);
Abstract

The optimal configuration of a number of optional pipeline stages within the data paths of systems-on-chip is determined by application of a solver. The solver includes variables such as: the placement of modules physically within the floorplan of the chip; the signal propagation time; the logic gate switching time; the arrival time, after a clock edge, of a signal at each module port; the arrival time at each pipeline stage; and the Boolean value of the state of activation of each optional pipeline stage. The optimal configuration ensures that a timing constraint is met, if possible, with the lowest possible cost of pipeline stages.


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