The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 18, 2015
Filed:
Dec. 27, 2012
Tak M. Mak, Union City, CA (US);
Christopher J. Nelson, Gilbert, AZ (US);
David J. Zimmerman, El Dorado Hills, CA (US);
Derek B. Feltham, Portland, OR (US);
Tak M. Mak, Union City, CA (US);
Christopher J. Nelson, Gilbert, AZ (US);
David J. Zimmerman, El Dorado Hills, CA (US);
Derek B. Feltham, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
I/O delay testing for devices utilizing on-chip delay generation. An embodiment of an apparatus includes I/O buffer circuits, at least one of the buffer circuits including a transmitter and a receiver that are coupled for loop-back testing of the buffer circuit; and testing circuitry for the loop-back testing for the at least one buffer circuit, the loop-back testing including determining whether test data transmitted by the transmitter of the buffer circuit matches test data received by the respective coupled receiver. The testing circuitry includes a delay line to provide delay values from a transmit clock signal for the testing of the at least one buffer circuit, a counter to provide a count to choose one of the plurality of delay values, and test logic for the loop-back testing.