The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2015

Filed:

Sep. 25, 2014
Applicant:

Avago Technologies General Ip (Singapore) Pte. Ltd., Singapore, SG;

Inventors:

Sunil Srinivasa, San Jose, CA (US);

Amaresh V. Malipatil, San Jose, CA (US);

Mohammad Shafiul Mobin, Orefield, PA (US);

Pervez Mirza Aziz, Dallas, TX (US);

Shiva Prasad Kotagiri, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H03D 3/24 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0016 (2013.01);
Abstract

A method for facilitating acquisition of a received reference clock signal in a CDR system includes steps of: initializing an integral register in a digital loop filter of the CDR system by setting a current value of the integral register to a first value; determining a number of mislock events occurring in a CDR loop of the CDR system, a mislock event being indicative of an unlocked state of the CDR loop; adjusting the current value of the integral register, when the number of mislock events is non-zero, by a second value to generate a new current value, the second value being a function of a negation of the current value of the integral register; and repeating the steps of determining the number of mislock events and adjusting the current value of the integral register until the number of mislock events is zero.


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