The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2015

Filed:

Dec. 06, 2011
Applicants:

James E. Jaussi, Hillsboro, OR (US);

Bruce E. Pederson, Beaverton, OR (US);

Howard L. Heck, Hillsboro, OR (US);

Stephen R. Mooney, Mapleton, UT (US);

Inventors:

James E. Jaussi, Hillsboro, OR (US);

Bruce E. Pederson, Beaverton, OR (US);

Howard L. Heck, Hillsboro, OR (US);

Stephen R. Mooney, Mapleton, UT (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01); H03K 19/00 (2006.01); H01R 13/66 (2006.01); H01R 24/60 (2011.01); H01R 25/00 (2006.01); H01R 12/72 (2011.01);
U.S. Cl.
CPC ...
H03K 19/0008 (2013.01); H01R 13/6658 (2013.01); H01R 24/60 (2013.01); H01R 25/006 (2013.01); H03K 19/0175 (2013.01); H01R 12/722 (2013.01); H01R 12/727 (2013.01);
Abstract

Disclosed is a scalable input/output interface that has multiple bays and includes a housing surrounding a plurality of pairs of substrates. A first substrate of the pair of substrates may have a first contact surface and a second substrate of the pair of substrates may have a second contact surface that opposes the first contact surface, wherein each substrate has a connection edge. At least one integrated buffer can be coupled to either the first side or the second side of each substrate. A plurality of rows of contacts can be coupled to the opposing surfaces of each substrate of the pair of substrates, wherein each row of contacts can be stacked substantially parallel to the connection edge. Each connection edge can also be coupled to a separate integrated buffer.


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