Fabrication of low threshold voltage and inversion oxide thickness scaling for a high-k metal gate p-type mosfet

Abstract

A method of forming a semiconductor structure. The semiconductor structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in Tand Vof the pFET, while scaling Tinv and maintaining Vt for the nFET, resulting in the Vof the pFET becoming closer to the Vof a similarly constructed nFET with scaled Tvalues.