The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2015

Filed:

Jul. 24, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Andres Bryant, South Burlington, VT (US);

Lyndon R. Logan, Poughkeepsie, NY (US);

Edward J. Nowak, Essex Juntion, VT (US);

Robert R. Robison, Colchester, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78 (2013.01); H01L 27/1203 (2013.01); H01L 29/66666 (2013.01); H01L 29/7841 (2013.01); H01L 27/10802 (2013.01);
Abstract

Approaches for zero capacitance memory cells are provided. A method of manufacturing a semiconductor structure includes forming a channel region by doping a first material with a first type of impurity. The method includes forming source/drain regions by doping a second material with a second type of impurity different than the first type of impurity, wherein the second material has a smaller bandgap than the first material. The method includes forming lightly doped regions between the channel region and the source/drain regions, wherein the lightly doped regions include the second material. The method includes forming a gate over the channel region, wherein the second material extends under edges of the gate.


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