The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2015

Filed:

Oct. 22, 2012
Applicant:

Newport Fab, Llc, Newport Beach, CA (US);

Inventors:

Volker Blaschke, Irvine, CA (US);

Todd Thibeault, Costa Mesa, CA (US);

Chris Cureton, Laguna Beach, CA (US);

Paul Hurwitz, Irvine, CA (US);

Arjun Kar-Roy, Irvine, CA (US);

David Howard, Irvine, CA (US);

Marco Racanelli, Santa Ana, CA (US);

Assignee:

Newport Fab, LLC, Newport Beach, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/74 (2006.01);
U.S. Cl.
CPC ...
H01L 21/743 (2013.01); H01L 2924/0002 (2013.01);
Abstract

According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.


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