The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2015

Filed:

Sep. 11, 2008
Applicant:

Avto Tavkhelidze, Tbilisi, GE;

Inventor:

Avto Tavkhelidze, Tbilisi, GE;

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/775 (2006.01); H01L 29/66 (2006.01); H01L 49/00 (2006.01); B82Y 10/00 (2011.01); H01L 29/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66977 (2013.01); B82Y 10/00 (2013.01); H01L 49/006 (2013.01); H01L 29/125 (2013.01); H01L 29/66439 (2013.01); H01L 29/775 (2013.01);
Abstract

A new type of Metal Oxide Semiconductor (MOS) transistor that works on the basis of the Quantum Interference Depression (QID) effect is disclosed. QID occurs inside an n-type semiconductor source-drain electrode of special geometry. Due to QID the Fermi level of said semiconductor increases locally inside the source drain electrode, thereby creating a localized potential energy barrier in the path of electrons moving from source to drain regions. The height of the barrier depends on the degree of QID. QID is in turn regulated by the gate voltage via the charge depletion and hence change in effective dimensions of the special geometry of the semiconductor electrode. A gate voltage modulated potential energy barrier and is thus formed whereby current in said MOS transistor is controlled.


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