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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9105576 B1

PDFFull Text
Date of Patent:
Aug. 11, 2015

Filed:

Aug. 11, 2014

Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same

Applicant:

Sandisk 3d Llc, Milpitas, CA (US);

Inventors:

Yung-Tin Chen, Santa Clara, CA (US);

Andrei Mihnea, San Jose, CA (US);

Roy E. Scheuerlein, Cupertino, CA (US);

Luca Fasoli, Campbell, CA (US);

Assignee:

SanDisk 3D LLC, Milpitas, CA (US);

Attorney:

Vierra Magen Marcus LLP

Primary Examiner:

Shaun Campbell

Assistant Examiner:

Raj R Gupta

Int. Cl.
CPC ...
H01L 47/00 (2006.01); H01L 27/24 (2006.01); G11C 11/56 (2006.01); G11C 13/00 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2481 (2013.01); G11C 11/5685 (2013.01); G11C 13/0007 (2013.01); G11C 13/0069 (2013.01); H01L 27/2409 (2013.01); H01L 27/2463 (2013.01); H01L 45/08 (2013.01); H01L 45/12 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/146 (2013.01); H01L 45/16 (2013.01); H01L 45/1608 (2013.01); G11C 2013/0073 (2013.01); G11C 2213/55 (2013.01); G11C 2213/56 (2013.01); G11C 2213/71 (2013.01); G11C 2213/72 (2013.01);
Abstract

In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.

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