The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2015

Filed:

Jul. 04, 2013
Applicant:

United Microelectronics Corporation, Hsinchu, TW;

Inventor:

Hsin-Wen Chen, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/41 (2006.01); G11C 11/417 (2006.01); G11C 11/412 (2006.01); G11C 11/413 (2006.01); G11C 7/12 (2006.01);
U.S. Cl.
CPC ...
G11C 11/417 (2013.01); G11C 7/12 (2013.01); G11C 11/412 (2013.01); G11C 11/413 (2013.01);
Abstract

A memory cell array includes a bit line, a complementary bit line, a first operation voltage supply circuit, a second operation voltage supply circuit, a first memory cell and a second memory cell. The first operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a first operation voltage. The second operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a second operation voltage. The first memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the first operation voltage. The second memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the second operation voltage. The first and second memory cells are located in a same column in the memory cell array.


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