The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2015

Filed:

Apr. 01, 2010
Applicants:

Rakesh Dodeja, Portland, OR (US);

Neelam Chandwani, Portland, OR (US);

Chetan Hiremath, Portland, OR (US);

Udayan Mukherjee, Portland, OR (US);

Anthony Ambrose, Portland, OR (US);

Inventors:

Rakesh Dodeja, Portland, OR (US);

Neelam Chandwani, Portland, OR (US);

Chetan Hiremath, Portland, OR (US);

Udayan Mukherjee, Portland, OR (US);

Anthony Ambrose, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3203 (2013.01); G06F 1/3225 (2013.01);
Abstract

A method to reduce memory power consumption for a computing platform includes inspecting an operating parameter associated with a resource of the computing platform that is updated by the resource of the computing platform during runtime of the computing platform. Memory power utilization is then predicted for the computing platform during the runtime of the computing platform based at least in part on the operating parameter. A current power state of at least one memory module resident on the computing platform is transitioned to one of a plurality of power states based on the predicting of the memory power utilization.


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