The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2015

Filed:

Dec. 20, 2013
Applicant:

Lam Research Corporation, Fremont, CA (US);

Inventors:

Harmeet Singh, Alameda, CA (US);

Christopher Kimball, San Jose, CA (US);

Keith Gaff, Alameda, CA (US);

Tyler Gloski, San Jose, CA (US);

Assignee:

LAM RESEARCH CORPORATION, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/683 (2006.01); H01T 23/00 (2006.01); H05F 3/02 (2006.01);
U.S. Cl.
CPC ...
H05F 3/02 (2013.01); H01L 21/6833 (2013.01);
Abstract

A semiconductor wafer processing apparatus for processing semiconductor wafers comprises a semiconductor wafer processing chamber in which a semiconductor wafer is processed, a process gas source in fluid communication with the processing chamber adapted to supply process gas into the processing chamber, a vacuum source adapted to exhaust process gas and byproducts of the processing from the processing chamber, and an electrostatic chuck assembly. The electrostatic chuck assembly comprises a support surface in a layer of ceramic material on which the semiconductor wafer is supported during processing of the wafer in the chamber, at least one electrostatic clamping electrode embedded in the layer of ceramic material, the at least one electrostatic clamping electrode operable to apply an electrostatic clamping force to the wafer on the support surface when an electrostatic clamping voltage is applied to the clamping electrode, and at least one declamping electrode embedded in the layer of ceramic material above the at least one electrostatic clamping electrode operable to provide a path for draining any residual charge between the wafer and the support surface when the electrostatic clamping voltage is no longer applied to the clamping electrode.


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