The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9098894 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 04, 2015

Filed:

Feb. 01, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Min-Sung Kuo, Zhubei, TW;

Chiun-Chieh Su, Hsin-Chu, TW;

To-Yu Chen, Tu-Ku Town, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K 9/00 (2006.01); G06T 7/00 (2006.01); G01N 21/956 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
G06T 7/001 (2013.01); G01N 21/95607 (2013.01); H01L 22/12 (2013.01); H01L 22/20 (2013.01); G06T 2207/30148 (2013.01);
Abstract

A method includes inspecting a wafer to find a first potential defect having a first wafer coordinate, and capturing a patch image of the first potential defect from the wafer. The patch image is compared with patterns of a wafer representation to find a first layout coordinate of a location in the wafer representation, wherein the location in the wafer representation corresponds to a location of the first potential defect in the wafer. A reference feature in the wafer representation is selected, wherein the reference feature in the wafer representation has a second layout coordinate. A coordinate difference between the first layout coordinate and the second layout coordinate is calculated. The coordinate difference is subtracted from the first wafer coordinate to calculate a second wafer coordinate of a reference feature in the wafer, wherein the reference feature in the wafer representation corresponds to the reference feature in the wafer.


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