The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2015
Filed:
Jul. 25, 2013
Method of cmos manufacturing utilizing multi-layer epitaxial hardmask films for improved epi profile
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Deborah Jean Riley, Murphy, TX (US);
Seung-Chul Song, Dallas, TX (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823807 (2013.01); H01L 21/82385 (2013.01); H01L 21/823814 (2013.01); H01L 21/823864 (2013.01);
Abstract
An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated silane reagent. A second layer of the hard mask is silicon nitride formed on the first layer using halogen-free reagents. After source/drain cavities are etched in the PMOS transistors, a pre-epitaxial bake with hydrogen is performed. After SiGe epitaxial source/drain regions are formed, the hard mask is removed.