The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2015

Filed:

Mar. 12, 2013
Applicant:

Rf Micro Devices, Inc., Greensboro, NC (US);

Inventors:

Kevin Wesley Kobayashi, Redondo Beach, CA (US);

Haldane S. Henry, Greensboro, NC (US);

Andrew P. Ritenour, Colfax, NC (US);

Assignee:

RF Micro Devices, Inc., Greensboro, NC (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 29/423 (2006.01); H01L 29/812 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/778 (2006.01); H01L 29/16 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42316 (2013.01); H01L 29/402 (2013.01); H01L 29/41725 (2013.01); H01L 29/66462 (2013.01); H01L 29/66477 (2013.01); H01L 29/7787 (2013.01); H01L 29/812 (2013.01); H01L 29/1608 (2013.01); H01L 29/2003 (2013.01);
Abstract

Methods for fabricating a field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends are disclosed. The methods provide field effect transistors that each include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. At least one method includes etching at least one gate channel into the passivation layer with a predetermined slope that reduces electric fields at a gate edge. Other methods include steps for fabricating a sloped gate foot, a round end, and/or a chamfered end to further improve high voltage operation.


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