The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9093376 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 28, 2015

Filed:

Oct. 24, 2012
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Hemanth Jagannathan, Guilderland, NY (US);

Sanjay C. Mehta, Niskayuna, NY (US);

Junli Wang, Singerlands, NY (US);

Chun-Chen Yeh, Clifton Park, NY (US);

Stefan Schmitz, Century Drive, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28132 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/78 (2013.01); H01L 29/785 (2013.01);
Abstract

A method for fabricating a field effect transistor device includes depositing a hardmask over a semiconductor layer depositing a metallic alloy layer over the hardmask, defining a semiconductor fin, depositing a dummy gate stack material layer conformally on exposed portions of the fin, patterning a dummy gate stack by removing portions of the dummy gate stack material using an etching process that selectively removes exposed portions of the dummy gate stack without appreciably removing portions of the metallic alloy layer, removing exposed portions of the metallic alloy layer, forming spacers adjacent to the dummy gate stack, forming source and drain regions on exposed regions of the semiconductor fin, removing the dummy gate stack, removing exposed portions of the metallic alloy layer, and forming a gate stack conformally over exposed portions of the insulator layer and the semiconductor fin.


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