The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2015
Filed:
Mar. 07, 2012
Shiro Hino, Tokyo, JP;
Naruhisa Miura, Tokyo, JP;
Akihiko Furukawa, Tokyo, JP;
Yukiyasu Nakao, Tokyo, JP;
Tomokatsu Watanabe, Tokyo, JP;
Masayoshi Tarutani, Tokyo, JP;
Yuji Ebiike, Tokyo, JP;
Masayuki Imaizumi, Tokyo, JP;
Sunao Aya, Tokyo, JP;
Shiro Hino, Tokyo, JP;
Naruhisa Miura, Tokyo, JP;
Akihiko Furukawa, Tokyo, JP;
Yukiyasu Nakao, Tokyo, JP;
Tomokatsu Watanabe, Tokyo, JP;
Masayoshi Tarutani, Tokyo, JP;
Yuji Ebiike, Tokyo, JP;
Masayuki Imaizumi, Tokyo, JP;
Sunao Aya, Tokyo, JP;
Mitsubishi Electric Corporation, Tokyo, JP;
Abstract
A semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same. A semiconductor device according to the present invention comprises a drift layer formed on a semiconductor substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layer and each of the first well regions, a gate electrode selectively formed on the gate insulating film, a source contact hole penetrating through the gate insulating film and reaching the inside of each of the first well regions, and a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains.