The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2015

Filed:

Oct. 22, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Brian J. Greene, Wappingers Falls, NY (US);

Augustin J. Hong, White Plains, NY (US);

Byeong Y. Kim, Lagrangeville, NY (US);

Dan M. Mocuta, Lagrangeville, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/027 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 21/18 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02636 (2013.01); H01L 21/0262 (2013.01); H01L 21/02433 (2013.01); H01L 21/02532 (2013.01); H01L 21/182 (2013.01); H01L 29/165 (2013.01); H01L 29/785 (2013.01); H01L 29/78603 (2013.01);
Abstract

A dielectric material layer is formed on a semiconductor-on-insulator (SOI) substrate including a top semiconductor layer containing a first semiconductor material. An opening is formed within the dielectric material layer, and a trench is formed in the top semiconductor layer within the area of the opening by an etch. A second semiconductor material is deposited to a height above the top surface of the top semiconductor layer employing a selective epitaxy process. Another dielectric material layer can be deposited, and another trench can be formed in the top semiconductor layer. Another semiconductor material can be deposited to a different height employing another selective epitaxy process. The various semiconductor material portions can be patterned to form semiconductor fins having different heights and/or different compositions.


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