The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2015

Filed:

Dec. 13, 2013
Applicants:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Stmicroelectronics SA, Montrouge, FR;

Inventors:

Bastien Giraud, Grenoble, FR;

Philippe Flatresse, Lapierre, FR;

Matthieu Le Boulaire, Saint Martin le Vinoux, FR;

Jean-Philippe Noel, Montbonnot Saint Martin, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); G06F 17/5068 (2013.01); G06F 17/5077 (2013.01); H01L 21/84 (2013.01);
Abstract

An IC including first and second FDSOI UTBOX cells arranged in a row, the first having an nMOS transistor arranged plumb with and above a ground plane and an N-type well, and a pMOS transistor arranged plumb with and above a ground plane and a P-type well, the N-type well and the P-type well being arranged on either side of a row axis, wherein the second includes a diode protecting against antenna effects or a well tap cell, the second cell comprising a P-type well arranged in the alignment of the P-type well of the pMOS transistor and comprising an N-type well arranged in the alignment of the N-type well of the nMOS transistor, the second cell comprising a metal connection coupled to its P-type well and coupled to a higher-level metal connection element arranged plumb with the N-type well, the metal connection extending on either side of the axis.


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