The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2015
Filed:
Dec. 14, 2011
Zeev Sperber, Zichron Yakov, IL;
Shachar Finkelstein, Yokneam Illit, IL;
Gregory Pribush, Haifa, IL;
Amit Gradstein, Binyamina, IL;
Guy Bale, Haifa, IL;
Thierry Pons, Hadera, IL;
Zeev Sperber, Zichron Yakov, IL;
Shachar Finkelstein, Yokneam Illit, IL;
Gregory Pribush, Haifa, IL;
Amit Gradstein, Binyamina, IL;
Guy Bale, Haifa, IL;
Thierry Pons, Hadera, IL;
Intel Corporation, Santa Clara, CA (US);
Abstract
Methods and apparatus are provided for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one example a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one example a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.