The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2015

Filed:

Jun. 01, 2011
Applicants:

Xuefeng Liu, South Burlington, VT (US);

Robert M. Rassel, Colchester, VT (US);

Steven H. Voldman, South Burlington, VT (US);

Inventors:

Xuefeng Liu, South Burlington, VT (US);

Robert M. Rassel, Colchester, VT (US);

Steven H. Voldman, South Burlington, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 21/762 (2006.01); H01L 27/12 (2006.01); H01L 21/8238 (2006.01); H01L 21/8249 (2006.01); H01L 27/06 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 21/84 (2013.01); H01L 21/76243 (2013.01); H01L 21/76264 (2013.01); H01L 21/8249 (2013.01); H01L 21/823807 (2013.01); H01L 27/0635 (2013.01); H01L 27/0652 (2013.01); H01L 27/092 (2013.01); H01L 27/1203 (2013.01); H01L 27/1207 (2013.01);
Abstract

Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.


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