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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9087771 B1

PDFFull Text
Date of Patent:
Jul. 21, 2015

Filed:

Feb. 10, 2014

Method for manufacturing semiconductor device, semiconductor device and jig for forming wiring

Applicant:

Tokyo Electron Limited, Minato-ku, JP;

Inventors:

Haruo Iwatsu, Koshi, JP;

Toshiyuki Matsumoto, Koshi, JP;

Assignee:

TOKYO ELECTRON LIMITED, Minato-ku, JP;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Christine Enad

Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 27/06 (2006.01); H01L 21/768 (2006.01); H01L 23/525 (2006.01); H01L 23/544 (2006.01); H01L 25/065 (2006.01); H01L 21/683 (2006.01); H01L 21/288 (2006.01);
U.S. Cl.
CPC ...
H01L 24/25 (2013.01); H01L 21/2885 (2013.01); H01L 21/6835 (2013.01); H01L 21/76838 (2013.01); H01L 21/76892 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/525 (2013.01); H01L 23/544 (2013.01); H01L 24/19 (2013.01); H01L 24/82 (2013.01); H01L 25/0657 (2013.01); H01L 27/0688 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68381 (2013.01); H01L 2223/5444 (2013.01); H01L 2223/5448 (2013.01); Y10T 29/532 (2015.01);
Abstract

A method for manufacturing a semiconductor device includes: forming a structure including a substrate, a device layer formed on the substrate, a pair of through-hole electrodes penetrating through the substrate in the thickness direction of the substrate, a pair of vertical electrodes extending in the thickness direction of the substrate and reaching to one surface of the substrate, and a shared wiring connecting the pair of vertical electrodes in the device layer; forming a connection wiring connecting one of the through-hole electrodes and one of the vertical electrodes; and stacking the structure and a second substrate such that an electrode of the second substrate is connected to a through-hole electrode which is not connected to the connection wiring among the pair of through-hole electrodes.

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