The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2015
Filed:
Aug. 06, 2013
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
John Lin, Chelmsford, MA (US);
Philip L. Hower, Concord, MA (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 29/06 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0646 (2013.01); H01L 21/823878 (2013.01); H01L 21/823892 (2013.01); H01L 27/0251 (2013.01); H01L 27/092 (2013.01); H01L 27/0629 (2013.01);
Abstract
An integrated circuit (IC) includes a substrate having a p-type semiconductor surface. A first nwell includes an area surrounding a first plurality of semiconductor devices formed in the semiconductor surface having a first n-buried layer (NBL) thereunder. A vertical diode formed in the semiconductor surface surrounds the first nwell including a pwell on top of a floating NBL ring. A second nwell formed in the semiconductor surface includes an area surrounding the floating NBL ring and surrounds a second plurality of semiconductor devices having a second NBL thereunder.