The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2015

Filed:

Nov. 01, 2013
Applicant:

Ps4 Luxco S.a.r.l., Luxembourg, LU;

Inventors:

Hideyuki Yoko, Tokyo, JP;

Naohisa Nishioka, Tokyo, JP;

Chikara Kondo, Tokyo, JP;

Ryuji Takishita, Tokyo, JP;

Assignee:

PS4 Luxco S.a.r.l., Luxembourg, LU;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/22 (2006.01); G06F 1/10 (2006.01); G11C 5/02 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G06F 1/10 (2013.01); G11C 5/02 (2013.01); G11C 29/02 (2013.01); G11C 29/023 (2013.01); G11C 29/025 (2013.01); G11C 29/028 (2013.01); G11C 29/50012 (2013.01); H01L 2224/16145 (2013.01); H01L 2924/01037 (2013.01); H01L 2924/01055 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A semiconductor device includes an interface chip including: an internal data terminal, and a timing data storage circuit configured to output a plurality of timing set signals, and a plurality of core chips stacked with one another, each of the core chips including a plurality of memory cells, an output control circuit coupled to the timing data storage circuit of the interface chip, the output control circuit being configured to receive a corresponding one of the timing set signals and to output an output timing signal in response to the corresponding one of the timing set signals, and a data output circuit coupled to the internal data terminal of the interface chip, the data output circuit being configured to output data in response to the output timing signal, the data being derived from a corresponding one of the memory cells.


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