The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2015

Filed:

Mar. 01, 2013
Applicant:

Enraytek Optoelectronics Co., Ltd., Shanghai, CN;

Inventors:

Lujun Yao, Shanghai, CN;

Deyuan Xiao, Shanghai, CN;

Richard Ru-Gin Chang, Shanghai, CN;

Hongbo Yu, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/20 (2006.01); H01L 21/36 (2006.01); H01L 33/00 (2010.01); H01L 27/15 (2006.01); H01L 33/44 (2010.01); H01L 33/06 (2010.01); H01L 33/42 (2010.01); H01L 21/02 (2006.01); H01L 33/62 (2010.01); H01L 33/20 (2010.01);
U.S. Cl.
CPC ...
H01L 33/0075 (2013.01); H01L 27/156 (2013.01); H01L 33/06 (2013.01); H01L 33/42 (2013.01); H01L 33/44 (2013.01); H01L 21/0254 (2013.01); H01L 21/02458 (2013.01); H01L 21/02647 (2013.01); H01L 33/007 (2013.01); H01L 33/20 (2013.01); H01L 33/62 (2013.01); H01L 2924/0002 (2013.01); H01L 2933/0016 (2013.01); H01L 2933/0025 (2013.01); H01L 2933/0033 (2013.01);
Abstract

A method for manufacturing a deep isolation trench () and a method for manufacturing a high-voltage LED chip. Steps of the method for manufacturing a deep isolation trench () are as follows: forming a mask layer () on a substrate (), and forming, in the mask layer, through etching, multiple windows () isolated from each other, the bottom of each window exposing the substrate; with epitaxial lateral overgrowth, forming an epitaxial structure () inside each window and a part of the mask layer around the window, respectively, each epitaxial structure having a trapezoidal cross section with a long bottom and a short top, and a gap between adjacent epitaxial structures forming a first deep trench (); etching each epitaxial structure, forming a first shoulder () and a second shoulder () at both sides of each epitaxial structure, respectively, and forming a deep isolation trench above the mask layer between the adjacent epitaxial structures. The method for manufacturing a high-voltage LED chip is capable of decreasing preparation cost of the deep isolation trench in the high-voltage LED chip, and increasing continuity and compactness interconnection performance of an insulation isolation dielectric layer and an interconnection electrode layer between deep isolation trenches within a high-voltage LED chip.


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