The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2015

Filed:

Apr. 28, 2014
Applicant:

Avalanche Technology, Inc., Fremont, CA (US);

Inventors:

Ravishankar Tadepalli, Fremont, CA (US);

Rajiv Yadav Ranjan, San Jose, CA (US);

Mehdi Asnaashari, Danville, CA (US);

Ngon Van Le, Fremont, CA (US);

Parviz Keshtbod, Los Altos Hills, CA (US);

Assignee:

AVALANCHE TECHNOLOGY, INC., Fremont, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); G06F 12/00 (2006.01); G11C 11/14 (2006.01); G06F 12/02 (2006.01); G11C 11/15 (2006.01); G11C 11/16 (2006.01); G11C 14/00 (2006.01); H01L 27/22 (2006.01); G11C 13/00 (2006.01); G11C 11/00 (2006.01); G11C 13/02 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G11C 11/005 (2013.01); G11C 11/15 (2013.01); G11C 11/16 (2013.01); G11C 13/0002 (2013.01); G11C 13/0004 (2013.01); G11C 14/00 (2013.01); H01L 27/224 (2013.01); G11C 11/22 (2013.01); G11C 13/025 (2013.01); G11C 2213/71 (2013.01);
Abstract

A hybrid non-volatile memory device includes a non-volatile random access memory (NVRAM) having an array of magnetic memory elements, the NVRAM being bit-accessible. The hybrid non-volatile device further includes a non-volatile page-mode memory (PMM) made of resistive memory and organized into pages, the non-volatile PMM being page-accessible. Further included in the hybrid non-volatile memory device is a direct memory access (DMA) engine that is coupled to the NVRAM and the non-volatile PMM and transfers data between the NVRAM and the non-volatile PMM during a DMA operation.


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