The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2015

Filed:

Sep. 10, 2013
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Toan Thanh Nguyen, San Jose, CA (US);

Thungoc M. Tran, San Jose, CA (US);

Sergey Shumarayev, San Leandro, CA (US);

Arch Zaliznyak, San Jose, CA (US);

Shoujun Wang, Ottawa, CA;

Ramanand Venkata, San Francisco, CA (US);

Chong H. Lee, San Ramon, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 9/00 (2006.01); H03K 19/00 (2006.01); H03K 19/177 (2006.01); H04L 7/00 (2006.01); H04L 7/033 (2006.01); H04L 25/02 (2006.01); H04L 1/24 (2006.01);
U.S. Cl.
CPC ...
H03K 19/00 (2013.01); H04L 7/0008 (2013.01); H04L 7/033 (2013.01); H04L 25/0266 (2013.01); H04L 1/243 (2013.01); H03K 19/17744 (2013.01); H03M 9/00 (2013.01);
Abstract

Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device ('PLD') or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).


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