The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2015
Filed:
Jul. 06, 2012
Applicants:
Long-shih Lin, Zhubei, TW;
Kun-ming Huang, Taipei, TW;
Ming-yi Lin, Hsinchu, TW;
Inventors:
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 29/739 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7394 (2013.01); H01L 29/66325 (2013.01); H01L 29/42368 (2013.01); H01L 29/0634 (2013.01); H01L 29/0696 (2013.01); H01L 29/0847 (2013.01); H01L 29/1095 (2013.01);
Abstract
A metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly a lateral insulated gate bipolar junction transistor (LIGBT), and a method of making it are provided in this disclosure. The device includes a silicon-on-insulator (SOI) substrate having a drift region, two oppositely doped well regions in the drift region, two insulating structures over and embedded in the drift region and second well region, a gate structure, and a source region in the second well region over a third well region embedded in the second well region. The third well region is disposed between the gate structure and the second insulating structure.