The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2015

Filed:

Jun. 27, 2014
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventor:

Wen-Yueh Jang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); H01L 27/115 (2006.01); H01L 27/105 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 27/11519 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01); H01L 27/1052 (2013.01);
Abstract

A 3-D memory is provided. Each word line layer has word lines and gaps alternately arranged along a first direction. Gaps include first group and second group of gaps alternately arranged. A first bit line layer is on word line layers and has first bit lines along a second direction. A first conductive pillar array through word line layers connects the first bit line layer and includes first conductive pillars in first group of gaps. A first memory element is between a first conductive pillar and an adjacent word line. A second bit line layer is below word line layers and has second bit lines along the second direction. A second conductive pillar array through word line layers connects the second bit line layer and includes second conductive pillars in second group of gaps. A second memory element is between a second conductive pillar and an adjacent word line.


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