The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2015

Filed:

Dec. 12, 2012
Applicants:

Dongping Wu, Shanghai, CN;

Peng Xu, Shanghai, CN;

Wei Zhang, Shanghai, CN;

Shi-li Zhang, Stockholm, SE;

Inventors:

Dongping Wu, Shanghai, CN;

Peng Xu, Shanghai, CN;

Wei Zhang, Shanghai, CN;

Shi-Li Zhang, Stockholm, SE;

Assignee:

FUDAN UNIVERSITY, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/285 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28518 (2013.01); H01L 29/66742 (2013.01); H01L 29/786 (2013.01); H01L 21/324 (2013.01); H01L 29/665 (2013.01); H01L 29/66575 (2013.01); H01L 29/66643 (2013.01);
Abstract

A metal silicide thin film and ultra-shallow junctions and methods of making are disclosed. In the present disclosure, by using a metal and semiconductor dopant mixture as a target, a mixture film is formed on a semiconductor substrate using a physical vapor deposition (PVD) process. The mixture film is removed afterwards by wet etching, which is followed by annealing to form metal silicide thin film and ultra-shallow junctions. Because the metal and semiconductor dopant mixture is used as a target to deposit the mixture film, and the mixture film is removed by wet etching before annealing, self-limiting, ultra-thin, and uniform metal silicide film and ultra-shallow junctions are formed concurrently in semiconductor field-effect transistor fabrication processes, which are suitable for field-effect transistors at the 14 nm, 11 nm, or even further technology node.


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