The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2015

Filed:

Nov. 12, 2012
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Nima Mokhlesi, Los Gatos, CA (US);

Mohan V. Dunga, Santa Clara, CA (US);

Man Mui, Santa Clara, CA (US);

Assignee:

SANDISK TECHNOLOGIES INC., Plano, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/26 (2006.01); G11C 16/24 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 16/24 (2013.01); G11C 11/5642 (2013.01); G11C 16/0483 (2013.01); G11C 16/3427 (2013.01); H01L 27/11524 (2013.01);
Abstract

A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. One set of embodiments avoid unwanted boosting during read operations by keeping the channels of the memory cells connected to word lines on the drain side of the selected word line biased at a fixed potential.


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