The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2015

Filed:

Dec. 13, 2012
Applicant:

Intermolecular, Inc., San Jose, CA (US);

Inventors:

Mankoo Lee, Fremont, CA (US);

Tony Chiang, Campbell, CA (US);

Dipankar Pramanik, Saratoga, CA (US);

Assignee:

Intermolecular, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0033 (2013.01); G11C 13/0002 (2013.01); G11C 13/003 (2013.01); G11C 13/0007 (2013.01); G11C 13/0069 (2013.01); G11C 2213/72 (2013.01); G11C 2213/76 (2013.01); G11C 2213/77 (2013.01); G11C 2213/79 (2013.01);
Abstract

Non linear current response circuits can be used in embedded resistive memory cell for reducing power consumption, together with improving reliability of the memory array. The non linear current response circuits can include two back to back leaky PIN diodes, two parallel anti-directional PIN diodes, two back to back Zener-type metal oxide diodes, or ovonic switching elements, along with current limiting resistor for standby power reduction at the low voltage region. Also, the proposed embedded ReRAM implementation methods based upon 1T2D1R scheme can be integrated into the advanced FEOL process technologies including vertical pillar transistor and/or 3D fin-shaped field effect transistor (FinFET) for realizing a highly compact cell density.


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