The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2015
Filed:
Sep. 26, 2011
Jonathan (Son) Hung Tran, Murphy, TX (US);
Raguram Damodaran, Plano, TX (US);
Abhijeet Ashok Chachad, Plano, TX (US);
Joseph Raymond Michael Zbiciak, Arlington, TX (US);
Jonathan (Son) Hung Tran, Murphy, TX (US);
Raguram Damodaran, Plano, TX (US);
Abhijeet Ashok Chachad, Plano, TX (US);
Joseph Raymond Michael Zbiciak, Arlington, TX (US);
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Abstract
This invention optimizes DMA writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two controller detects that a line is valid and dirty in level one, the level two memory need not update its copy of the data. Level one memory will replace the level two copy with a victim writeback at a future time. Thus the level two memory need not store write a copy. This limits the number of DMA writes to level two directly addressable memory and thus improves performance and minimizes dynamic power. This also frees the level two memory for other master/requestors.