The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2015
Filed:
Mar. 01, 2013
Intel Corporation, Santa Clara, CA (US);
Eric Fetzer, Loveland, CO (US);
Reid Riedlinger, Wellington, CO (US);
Don Soltis, Windsor, CO (US);
William Bowhill, Framingham, MA (US);
Satish Shrimali, Bangalore, IN;
Krishnakanth Sistla, Beaverton, OR (US);
Efraim Rotem, Haifa, IL;
Rakesh Kumar, Bangalore, IN;
Vivek Garg, Folsom, CA (US);
Alon Naveh, Ramat Hasharon, IL;
Lokesh Sharma, Bangalore, IL;
Intel Corporation, Santa Clara, CA (US);
Abstract
A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.