The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2015

Filed:

Dec. 16, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tien Chun Yang, San Jose, CA (US);

Yuwen Swei, Fremont, CA (US);

Chih-Chang Lin, San Jose, CA (US);

Chiang Pu, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H03K 19/0175 (2006.01); H03K 19/0185 (2006.01); H05K 13/00 (2006.01);
U.S. Cl.
CPC ...
H03K 19/017509 (2013.01); Y10T 29/49117 (2015.01); H03K 19/018521 (2013.01); H05K 13/0023 (2013.01);
Abstract

A method of making a level shifter includes coupling a driver stage between an input end and an output end, the driver stage comprising a first transistor and a second transistor. An inverter having an input is coupled with the input end. A third transistor having a gate end is coupled with an output of the inverter, the third transistor having a terminal coupled to a pumped voltage (VPP). Additionally, the method includes coupling a fourth transistor with the output end, the fourth transistor having a terminal coupled to the pumped voltage. A fifth transistor is coupled with the input end, the fifth transistor having a terminal coupled to the third and fourth transistors. A sixth transistor is coupled with the input end, the sixth transistor having a terminal.


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