The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2015

Filed:

Nov. 16, 2012
Applicant:

Suzhou Institute of Nano-tech and Nano-bionics of Chinese Academy of Science, Suzhou, CN;

Inventors:

Yong Cai, Suzhou, CN;

Guohao Yu, Suzhou, CN;

Zhihua Dong, Suzhou, CN;

Baoshun Zhang, Suzhou, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/778 (2013.01); H01L 29/42316 (2013.01); H01L 29/7787 (2013.01); H01L 29/1029 (2013.01); H01L 29/2003 (2013.01);
Abstract

A group III nitride high electron mobility transistor (HEMT) device comprises a source electrode (), a drain electrode (), a main gate (), a top gate (), an insulating dielectric layer () and a heterostructure, wherein the source electrode () and the drain electrode () are electrically connected via two-dimensional electron gas (2DEG) formed in the heterostructure; the heterostructure comprises a first semiconductor () and a second semiconductor (); the first semiconductor () is disposed between the source electrode () and drain electrode (); the second semiconductor () is formed on the surface of the first semiconductor () and is provided with a band gap wider than the first semiconductor (); the main gate () is disposed at the side of the surface of the second semiconductor () adjacent to the source electrode (), and is in Schottky contact with the second semiconductor (); the dielectric layer () is disposed on the surfaces of the second semiconductor () and the main gate () and between the source electrode () and the drain electrode (); the top gate () is formed on the surface of the dielectric layer (), at least one side edge of the top gate extends towards the direction of the source electrode () or the drain electrode (), and the orthographic projection of the top gate overlaps with the two side edges of the main gate (). When the HEMT device is at work, the main gate () and the top gate () are respectively controlled by a control signal. The device can effectively inhibit the 'current collapse effect'.


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