The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2015

Filed:

Apr. 30, 2012
Applicants:

Scott A. Segan, Allentown, PA (US);

Scott T. Van Horn, Shenandoah, PA (US);

Gary E. Hall, Danielsville, PA (US);

Matthew J. Gehman, Bally, PA (US);

Richard Muscavage, Gilbertsville, PA (US);

Inventors:

Scott A. Segan, Allentown, PA (US);

Scott T. Van Horn, Shenandoah, PA (US);

Gary E. Hall, Danielsville, PA (US);

Matthew J. Gehman, Bally, PA (US);

Richard Muscavage, Gilbertsville, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/10 (2006.01); H01L 23/52 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 23/5283 (2013.01); H01L 23/5286 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An integrated circuit power grid is provided with improved routing resources and bypass capacitance. A power grid for an integrated circuit comprises a plurality of thick metal layers having a plurality of metal traces, wherein at least one of the thick metal layers has a lower pitch than a substantial maximum pitch allowed under the design rules for a given integrated circuit fabrication technology. A power grid for an integrated circuit can also comprise a plurality of thin metal layers having a plurality of metal traces, wherein a plurality of the metal traces on different thin metal layers are connected by at least one via, wherein the at least one via is substantially surrounded by a metal trace on at least one thin metal level connected to a different power supply voltage than a power supply of one or more additional thin metal levels. The via can be positioned, for example, at an intersection of a given standard cell row and a given vertical strap.


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